PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 170

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
14.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to trans-
mit/receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the SSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
14.9
A Reset disables the SSP module and terminates the
current transfer.
TABLE 14-2:
DS41250E-page 168
0Bh,8Bh.
10Bh,18Bh
0Ch
13h
14h
87h
8Ch
85h
94h
Legend:
Address
Sleep Operation
Effects of a Reset
INTCON
PIR1
SSPBUF
SSPCON
TRISC
PIE1
TRISA
SSPSTAT
x = unknown, u = unchanged,
Name
REGISTERS ASSOCIATED WITH SPI™ OPERATION
Synchronous Serial Port Receive Buffer/Transmit Register
TRISC7
TRISA7
WCOL
EEIF
EEIE
Bit 7
SMP
GIE
SSPOV
TRISC6
TRISA6
PEIE
ADIF
ADIE
Bit 6
CKE
-
= unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
TRISC5
SSPEN
TRISA5
RCIE
RCIF
Bit 5
T0IE
D/A
TRISC4
TRISA4
Preliminary
INTE
Bit 4
TXIF
CKP
TXIE
P
TRISC3
SSPM3
TRISA3
SSPIE
SSPIF
RBIE
Bit 3
S
14.10 Bus Mode Compatibility
Table 14-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 14-1:
There is also a SMP bit which controls when the data is
sampled.
Mode Terminology
Standard SPI™
CCP1IF
TRISC2
CCP1IE
SSPM2
TRISA2
Bit 2
T0IF
R/W
0, 0
0, 1
1, 0
1, 1
TMR2IE
TMR2IF
TRISC1
SSPM1
TRISA1
INTF
Bit 1
UA
SPI™ BUS MODES
TMR1IE
TMR1IF
TRISC0
SSPM0
TRISA0
RBIF
Bit 0
© 2005 Microchip Technology Inc.
BF
CKP
Control Bits State
0000 000x 0000 000x
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0
0
1
1
Value on:
POR,
BOR
Value on
all other
CKE
Resets
1
0
1
0