PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 190

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
16.3
The on-chip POR circuit holds the chip in Reset until
V
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to V
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
V
cations” for details. If the BOR is enabled, the maxi-
mum rise time specification does not apply. The BOR
circuitry will keep the device in Reset until V
V
(BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
16.3.1
PIC16F917/916/914/913 has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from early devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to V
network, as shown in Figure 16-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
cleared, MCLR is internally tied to V
weak pull-up is enabled for the MCLR pin. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
DS41250E-page 188
DD
DD
BOR
Note:
is required. See Section 19.0 “Electrical Specifi-
has reached a high enough level for proper
(see
Power-on Reset
The POR circuit does not produce an
internal Reset when V
re-enable the POR, V
for a minimum of 100 s.
MCLR
Section 16.3.3
“Brown-Out
DD
DD
. The use of an RC
DD
DD
must reach Vss
and an internal
declines. To
DD
DD
reaches
Reset
. This
Preliminary
FIGURE 16-2:
16.3.2
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 4.4 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the V
uration bit, PWRTE, can disable (if set) or enable (if
cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
• V
• Temperature variation
• Process variation
See
“Electrical Specifications”).
DD
DC
variation
V
DD
R1
1 k
POWER-UP TIMER (PWRT)
C1
0.1 F
(optional, not critical)
DD
parameters
to rise to an acceptable level. A config-
or greater)
RECOMMENDED
CIRCUIT
© 2005 Microchip Technology Inc.
for
details
MCLR
PIC16F917/916/
914/913
(Section 19.0
MCLR