PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 266

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
Timing Parameter Symbology........................................... 228
Timing Requirements
TMR1H Register ................................................................. 85
TMR1L Register .................................................................. 85
TRISA
TRISA Register ................................................................... 32
TRISB
TRISB Register ................................................................... 42
TRISC
TRISC Register ................................................................... 51
DS41250E-page 264
Brown-out Reset Situations ...................................... 189
Capture/Compare/PWM............................................ 235
CLKO and I/O ........................................................... 231
Clock Synchronization .............................................. 176
Comparator Output ..................................................... 94
External Clock ........................................................... 229
Fail-Safe Clock Monitor (FSCM) ................................. 80
I
I
I
I
I
I
INT Pin Interrupt........................................................ 197
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 121
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 123
Reset, WDT, OST and Power-up Timer ................... 232
Slave Synchronization .............................................. 166
SPI Master Mode (CKE = 1, SMP = 1) ..................... 238
SPI Mode (Master Mode) .......................................... 165
SPI Mode (Slave Mode with CKE = 0) ...................... 167
SPI Mode (Slave Mode with CKE = 1) ...................... 167
SPI Slave Mode (CKE = 0) ....................................... 239
SPI Slave Mode (CKE = 1) ....................................... 239
Synchronous Reception (Master Mode, SREN) ....... 141
Synchronous Transmission....................................... 139
Synchronous Transmission (Through TXEN) ........... 139
Time-out Sequence
Timer0 and Timer1 External Clock ........................... 233
Timer1 Incrementing Edge.......................................... 86
Two Speed Start-up .................................................... 79
Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 111
Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 113
Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 115
Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 117
Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 119
Type-A/Type-B in Static Drive................................... 110
Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 112
Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 114
Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 116
Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 118
Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 120
USART Synchronous Receive (Master/Slave) ......... 235
USART Synchronous Transmission (Master/Slave) . 234
Wake-up from Interrupt ............................................. 202
I
I2C Bus Start/Stop Bits ............................................. 241
SPI Mode .................................................................. 240
Registers ..................................................................... 31
Registers ..................................................................... 41
Registers ..................................................................... 51
2
2
2
2
2
2
2
C Bus Data ............................................................. 241
C Bus Start/Stop Bits.............................................. 240
C Reception (7-bit Address) ................................... 171
C Slave Mode (Transmission, 10-bit Address) ....... 174
C Slave Mode with SEN = 0 (Reception,
C Transmission (7-bit Address) .............................. 173
C Bus Data ............................................................. 242
10-bit Address).................................................. 172
Case 1............................................................... 191
Case 2............................................................... 191
Case 3............................................................... 191
Preliminary
TRISD
TRISD Register................................................................... 60
TRISE
TRISE Register................................................................... 65
Two-Speed Clock Start-up Mode........................................ 78
TXSTA Register
U
UA..................................................................................... 160
Update Address bit, UA .................................................... 160
USART.............................................................................. 127
V
Voltage Reference. See Comparator Voltage Reference
VRCON Register .............................................................. 100
Registers .................................................................... 60
Registers .................................................................... 65
BRGH Bit .................................................................. 127
CSRC Bit .................................................................. 127
SYNC Bit .................................................................. 127
TRMT Bit................................................................... 127
TX9 Bit ...................................................................... 127
TX9D Bit ................................................................... 127
TXEN Bit ................................................................... 127
Address Detect Enable (ADDEN Bit)........................ 128
Asynchronous Mode ................................................. 131
Asynchronous Receive (9-bit Mode)......................... 136
Asynchronous Receive with Address Detect.
Asynchronous Receiver............................................ 134
Asynchronous Reception.......................................... 134
Asynchronous Transmitter........................................ 131
Baud Rate Generator (BRG) .................................... 129
Clock Source Select (CSRC Bit)............................... 127
Continuous Receive Enable (CREN Bit)................... 128
Framing Error (FERR Bit) ......................................... 128
Mode Select (SYNC Bit) ........................................... 127
Overrun Error (OERR Bit)......................................... 128
Receive Data, 9th Bit (RX9D Bit).............................. 128
Receive Enable, 9-bit (RX9 Bit) ................................ 128
Serial Port Enable (SPEN Bit) .......................... 127, 128
Single Receive Enable (SREN Bit) ........................... 128
Synchronous Master Mode....................................... 138
Synchronous Master Reception................................ 140
Synchronous Master Transmission .......................... 138
Synchronous Slave Mode......................................... 141
Synchronous Slave Reception.................................. 142
Synchronous Slave Transmit.................................... 141
Transmit Data, 9th Bit (TX9D) .................................. 127
Transmit Enable (TXEN Bit) ..................................... 127
Transmit Enable, Nine-bit (TX9 Bit) .......................... 127
Transmit Shift Register Status (TRMT Bit) ............... 127
(CV
REF
See Asynchronous Receive (9-bit Mode).
Baud Rate Formula .......................................... 129
Baud Rates, Asynchronous Mode (BRGH = 0) 130
Baud Rates, Asynchronous Mode (BRGH = 1) 130
High Baud Rate Select (BRGH Bit) .................. 127
Sampling........................................................... 129
Requirements, Synchronous Receive .............. 235
Requirements, Synchronous Transmission...... 235
Timing Diagram, Synchronous Receive ........... 235
Timing Diagram, Synchronous Transmission... 234
)
© 2005 Microchip Technology Inc.