PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 171

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.11 SSP I
The SSP module in I
slave functions, except general call support, and pro-
vides interrupts on Start and Stop bits in hardware to
facilitate firmware implementations of the master func-
tions. The SSP module implements the Standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC6/TX/CK/SCK/SCL/SEG9 pin, which is the clock
(SCL), and the RC7/RX/DT/SDI/SDA/SEG8 pin, which
is the data (SDA).
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 14-7:
The SSP module has five registers for the I
which are listed below.
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) – Not directly
• SSP Address Register (SSPADD)
© 2005 Microchip Technology Inc.
SCL/SEG9
RX/DT/
CK/SCK/
SEG8
RC6/TX/
RC7/
SDA/
accessible
SDI/
Read
Clock
2
Shift
C Operation
MSb
SSP BLOCK DIAGRAM
(I
2
Stop bit Detect
SSPADD Reg
SSPBUF Reg
Match Detect
SSPSR Reg
C mode, fully implements all
2
Start and
C™ MODE)
LSb
Write
(SSPSTAT reg)
Internal
Data Bus
2
Set, Reset
S, P bits
Addr Match
C operation,
Preliminary
PIC16F917/916/914/913
The SSPCON register allows control of the I
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I
Additional information on SSP I
found in the “PICmicro
Reference Manual” (DS33023).
14.12 Slave Mode
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<7:6> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a)
b)
In this case, the SSPSR register value is not loaded into
the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 14-3
shows the results of when a data transfer byte is received,
given the status of bits BF and SSPOV. The shaded cells
show the condition where user software did not properly
clear the overflow condition. Flag bit BF is cleared by
reading the SSPBUF register, while bit SSPOV is cleared
through software.
The SCL clock input must have a minimum high and
low for proper operation. For high and low times of the
I
SSP module, see Section 19.0 “Electrical Specifica-
tions”.
2
C specification, as well as the requirements of the
Stop bit interrupts enabled to support Firmware
Master mode
Stop bit interrupts enabled to support Firmware
Master mode
support Firmware Master mode; Slave is idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with Start and
C Slave mode (10-bit address), with Start and
C Start and Stop bit interrupts enabled to
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
2
C module.
2
C mode with the SSPEN bit set
®
2
C modes to be selected:
Mid-Range MCU Family
2
C
DS41250E-page 169
o
peration can be
2
C