PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 112
PIC16F913-I/SP
Manufacturer Part Number
PIC16F913-I/SP
Description
28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F913-ISP.pdf
(272 pages)
Specifications of PIC16F913-I/SP
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
7K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F913-I/SP
Manufacturer:
TI
Quantity:
212
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PIC16F917/916/914/913
9.7
LCD waveforms are generated so that the net AC
voltage across the dark pixel should be maximized and
the net AC voltage across the clear pixel should be
minimized. The net DC voltage across any pixel should
be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
The pixel signal (COM-SEG) will have no DC compo-
nent and it can take only one of the two rms values. The
higher rms value will create a dark pixel and a lower
rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
FIGURE 9-5:
DS41250E-page 110
COM0
LCD Waveform Generation
TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
COM0-SEG0
COM0-SEG1
COM0
SEG0
SEG1
Preliminary
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In Type-A waveform, the phase
changes within each common type, whereas in Type-B
waveform, the phase changes on each frame
boundary. Thus, Type-A waveform maintains 0 VDC
over a single frame, whereas Type-B waveform takes
two frames.
Figure 9-5 through Figure 9-15 provide waveforms for
static,
quarter-multiplex drives for Type-A and Type-B
waveforms.
Note 1: If Sleep has to be executed with LCD
1 Frame
2: When the LCD clock source is F
half-multiplex,
Sleep enabled (LCDCON<SLPEN> is
‘1’), then care must be taken to execute
Sleep only when V
‘0’.
if Sleep is executed, irrespective of the
LCDCON<SLPEN> setting, the LCD goes
into Sleep. Thus, take care to see that V
on all pixels is ‘0’ when Sleep is executed.
© 2005 Microchip Technology Inc.
one-third-multiplex
DC
on all the pixels is
OSC
/8192,
V
V
V
V
V
V
V
V
-V
V
1
0
1
0
1
0
1
0
0
1
and
DC
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