PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 175

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.12.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be
RC6/TX/CK/SCK/SCL/SEG9 is held low. The transmit
data must be loaded into the SSPBUF register, which
also
RC6/TX/CK/SCK/SCL/SEG9 should be enabled by
setting bit CKP (SSPCON<4>). The master must mon-
itor the SCL pin prior to asserting another clock pulse.
The slave devices may be holding off the master by
stretching the clock. The eight data bits are shifted out
on the falling edge of the SCL input. This ensures that
the SDA signal is valid during the SCL high time
(Figure 14-10).
FIGURE 14-10:
© 2005 Microchip Technology Inc.
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
sent
loads
S
TRANSMISSION
on
the
A7
1
Data in
sampled
the
SSPSR
A6
2
I
2
C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A5
Receiving Address
3
ninth
A4
4
register.
A3
5
bit,
A2
6
Then,
A1
and
7
R/W = 1
8
Preliminary
pin
pin
9
ACK
responds to SSPIF
while CPU
SCL held low
PIC16F917/916/914/913
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another occur-
rence of the Start bit. If the SDA line was low (ACK), the
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then pin
RC6/TX/CK/SCK/SCL/SEG9 should be enabled by
setting bit CKP.
D7
1
SSPBUF is written in software
D6
2
Cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
D5
3
D4
4
Transmitting Data
D3
5
D2
6
From SSP Interrupt
Service Routine
D1
7
DS41250E-page 173
D0
8
ACK
9
P