EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 98

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–6
Table 5–3. Clock Input Pin Connectivity to RCLK Networks
Clock Input Connections to PLLs
Table 5–4. Arria II GX Device PLLs and PLL Clock Pin Drivers
Clock Output Connections
Arria II GX Device Handbook, Volume 1
RCLK [12, 14, 16, 18, 20, 22]
RCLK [13, 15, 17, 19, 21, 23]
RCLK [24..35]
RCLK [36, 38, 40, 42, 44, 46]
RCLK [37, 39, 41, 43, 45, 47]
CLK[4..7]
CLK[8..11]
CLK[12..15]
Note to
(1) PLL_5 and PLL_6 are connected directly to CLK[8..11]. PLL_1, PLL_2, PLL_3 and PLL_4 are driven by the clock input pins
through a 4:1 multiplexer.
Dedicated Clock Input Pin (CLK pins)
Table
5–4:
Clock Resource
Table 5–3
Arria II GX devices. A given clock input pin can drive two adjacent RCLK networks to
create a dual-RCLK network.
Table 5–4
PLLs in Arria II GX devices can drive up to 24 RCLK networks and 8 GCLK networks.
For Arria II GX PLL connectivity to GCLK networks, refer to
Quartus
networks.
Table 5–5
Table 5–5. Arria II GX PLL Connectivity to GCLKs
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
®
Clock Network
II software automatically assigns PLL clock outputs to RCLK or GCLK
lists the connectivity between the dedicated clock input pins and RCLKs in
lists dedicated clock input pin connectivity to Arria II GX PLLs.
lists how the PLL clock outputs connect to GCLK networks.
—
—
—
—
v
4
—
—
v
1
—
—
—
—
v
5
—
—
v
v
1
(Note 1)
—
—
—
—
v
6
—
v
v
2
—
—
—
—
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
7
v
—
—
v
v
2
—
—
—
—
v
8
PLL Number
—
v
v
3
CLK (Pins)
—
—
—
—
—
—
v
9
v
v
PLL Number
3
10
—
—
—
—
v
—
—
v
4
Clock Networks in Arria II GX Devices
Table
—
—
v
v
© July 2010 Altera Corporation
4
11
—
—
—
—
v
5–5. The
12
—
—
—
—
—
—
v
v
5
—
—
—
v
5
13
—
—
—
—
v
v
—
—
14
—
—
—
—
v
6
—
—
—
v
6
15
—
—
—
—
v