EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 261
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Configuration Data Decompression
Configuration Data Decompression
© July 2010
Altera Corporation
1
1
Arria II GX devices support configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration or other memory devices and transmit this
compressed bitstream to Arria II GX devices. During configuration, the Arria II GX
device decompresses the bitstream in real time and programs its SRAM cells.
Preliminary data indicates that compression typically reduces the configuration
bitstream size by 35 to 55% based on the designs used.
Arria II GX devices support decompression in the FPP (when using a MAX II device
or microprocessor + flash), AS, and PS configuration schemes. The Arria II GX
decompression feature is not available in the JTAG configuration scheme.
When using FPP mode, the intelligent host must provide a DCLK that is ×4 the data
rate. Therefore, the configuration data must be valid for four DCLK cycles.
In PS mode, use the Arria II GX decompression feature, because sending compressed
configuration data reduces configuration time.
When you enable compression, the Quartus II software generates configuration files
with compressed configuration data. This compressed file reduces the storage
requirements in the configuration device or flash memory, and decreases the time
needed to transmit the bitstream to the Arria II GX device. The time required by a
Arria II GX device to decompress a configuration file is less than the time needed to
transmit the configuration data to the device.
There are two ways to enable compression for Arria II GX bitstreams: before design
compilation (in the Compiler Settings menu) and after design compilation (in the
Convert Programming Files window).
To enable compression in the project’s Compiler Settings menu, perform the following
steps:
1. On the Assignments menu, click Device to bring up the Settings dialog box.
2. After selecting your Arria II GX device, open the Device and Pin Options dialog
3. In the Configuration settings tab, enable the check box for Generate compressed
box.
bitstreams (as shown in
Figure
9–19).
Arria II GX Device Handbook, Volume 1
9–41
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