EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 61

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

DSP Block Overview
© July 2010
AIIGX51004-3.0
Altera Corporation
Arria
blocks optimized for DSP applications. These DSP blocks are the fourth generation of
hardwired, fixed-function silicon blocks dedicated to maximizing signal processing
capability and ease-of-use at the lowest silicon cost.
This chapter contains the following sections:
■
■
■
■
■
■
Many complex systems, such as WiMAX, 3GPP WCDMA, high-performance
computing (HPC), voice over Internet protocol (VoIP), H.264 video compression,
medical imaging, and HDTV, use sophisticated DSP techniques. Arria II GX devices
are ideally suited for these systems because the DSP blocks consist of a combination of
dedicated elements that perform multiplication, addition, subtraction, accumulation,
summation, and dynamic shift operations.
Arria II GX devices have two to four columns of DSP blocks that implement
multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift
functions. Architectural highlights of the Arria II GX DSP block include:
■
■
■
■
■
■
■
■
■
■
“DSP Block Overview”
“Simplified DSP Operation” on page 4–3
“Operational Modes Overview” on page 4–5
“DSP Block Resource Descriptions” on page 4–6
“Operational Mode Descriptions” on page 4–13
“Software Support for Arria II GX Devices” on page 4–32
High-performance, power-optimized, fully registered, and pipelined
multiplication operations
Natively supported 9-bit, 12-bit, 18-bit, and 36-bit word lengths
Natively supported 18-bit complex multiplications
Efficiently supported floating-point arithmetic formats (24-bits for single precision
and 53-bits for double precision)
Signed and unsigned input support
Built-in addition, subtraction, and accumulation units to efficiently combine
multiplication results
Cascading 18-bit input bus to form tap-delay line for filtering applications
Cascading 44-bit output bus to propagate output results from one block to the next
block without external logic support
Rich and flexible arithmetic rounding and saturation units
Efficient barrel shifter support

II GX devices have dedicated high-performance digital signal processing (DSP)
4. DSP Blocks in Arria II GX Devices
Arria II GX Device Handbook, Volume 1