EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 48
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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3–8
Single-Port RAM
Arria II GX Device Handbook, Volume 1
1
When using the memory blocks in ROM, single-port, simple dual-port, or true
dual-port mode, you can corrupt the memory contents if you violate the setup or hold
time on any of the memory block input registers. This applies to both read and write
operations.
All memory blocks support single-port mode. Single-port mode allows you to do
either one-read or one-write operation at a time. Simultaneous reads and writes are
not supported in single-port mode.
configuration.
Figure 3–8. Single-Port Memory
Note to
(1) You can implement two single-port memory blocks in a single M9K block. For more information, refer to
During a write operation, behavior of the RAM outputs is configurable. If you use the
read-enable signal and perform a write operation with the read enable de-activated,
the RAM outputs retain the values they held during the most recent active read
enable. If you activate read enable during a write operation, or if you are not using the
read-enable signal at all, the RAM outputs either show the new data being written,
the old data at that address, or a don’t care value.
Table 3–3
mode.
Table 3–3. Arria II GX Port Width Configurations for MLABs and M9K Blocks
Mode Support” on page
Figure
lists the possible port width configurations for memory blocks in single-port
3–8:
64 × 10
32 × 16
32 × 18
32 × 20
MLABs
64 × 8
64 × 9
3–4.
data[ ]
address[ ]
wren
byteena[]
addressstall
clockena
rden
aclr
inclock
(Note 1)
Figure 3–8
shows the single-port RAM
M9K Blocks
Chapter 3: Memory Blocks in Arria II GX Devices
512 × 16
512 × 18
256 × 32
256 × 36
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
outclock
© November 2009 Altera Corporation
q[]
Memory Modes
“Packed
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