EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 258
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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9–38
Table 9–11. Dedicated Configuration Pins on the Arria II GX Device (Part 3 of 4)
Arria II GX Device Handbook, Volume 1
nCE
nCEO
ASDO
nCSO
DCLK
Pin Name
(1)
(1)
(1)
User Mode
N/A
N/A
N/A
N/A
I/O
Configuration
schemes (PS,
Synchronous
configuration
FPP, AS)
Scheme
AS
AS
All
All
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Output (AS)
open-drain
Input (PS,
Pin Type
Output
Output
Output
Input
FPP)
Active-low chip enable. The nCE pin activates the device with
a low signal to allow configuration. The nCE pin must be held
low during configuration, initialization, and user mode. In
single device configuration, it must be tied low. In
multi-device configuration, nCE of the first device is tied low
while its nCEO pin is connected to nCE of the next device in
the chain.
The nCE pin must also be held low for successful JTAG
programming of the device.
Output that drives low when device configuration is complete.
In single-device configuration, this pin is left floating. In
multi-device configuration, this pin feeds the next device’s
nCE pin and is pulled high by an external 10-k resistor. The
nCEO of the last device in the chain is left floating.
The nCEO pin is powered by the V
bank in which the nCEO pin resides.
After configuration, nCEO is available as user I/O pins. The
state of the nCEO pin depends on the Dual-Purpose Pin
settings.
Control signal from the Arria II GX device to the serial
configuration device in AS mode used to read out
configuration data.
In AS mode, ASDO has an internal pull-up resistor that is
always active.
Output control signal from the Arria II GX device to the serial
configuration device in AS mode that enables the
configuration device.
In AS mode, nCSO has an internal pull-up resistor that is
always active.
In PS and FPP configuration, DCLK is the clock input used to
clock data from an external source into the target device. Data
is latched into the device on the rising edge of DCLK.
In AS mode, DCLK is an output from the Arria II GX device
that provides timing for the configuration interface. In AS
mode, DCLK has an internal pull-up resistor (typically 25 k)
that is always active.
After configuration, this pin by default is driven into an
inactive state. In schemes that use a control host, DCLK must
be driven either high or low, whichever is more convenient.
Toggling this pin after configuration does not affect the
configured device.
Description
© July 2010 Altera Corporation
CCIO
power supply of the
Device Configuration Pins
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