EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 191
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Transmitter
Differential Transmitter
Figure 8–3. Arria II GX LVDS Transmitter Block Diagram
Notes to
(1) In SDR and DDR modes, the data width is 1 and 2, respectively.
(2) The tx_in port has a maximum data width of 10.
Serializer
© July 2010
Figure
Altera Corporation
8–3:
tx_coreclock
Fabric
FPGA
tx_in
The serializer takes parallel data up to 10-bits wide from the FPGA fabric and
converts the parallel data to serial data before sending the serial data to the
differential output buffer. The differential output buffer supports programmable
pre-emphasis and programmable voltage output differential (V
drive out mini-LVDS and RSDS signaling levels.
LVDS transmitter.
The serializer takes parallel data from the FPGA fabric, clocks it into the parallel load
registers, and serializes it using the shift registers before sending the data to the
differential output buffer. The MSB of the parallel data is transmitted first. The
parallel load and shift registers are clocked by the high-speed clock running at the
serial data rate (diffioclk) and controlled by the load enable signal
(LVDS_LOAD_EN) generated from the PLL. You can statically set the serialization
factor to ×4, ×6, ×7, ×8, or ×10 using the ALTLVDS megafunction. The load enable
signal is derived from the serialization factor setting.
You can bypass the serializer to support DDR (×2) and SDR (×1) operations to achieve
a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data
output registers that can each operate in either DDR or SDR mode.
the serializer bypass path.
10
Center/Corner PLL
DIN
Serializer
3
DOUT
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
2
IOE
tx_inclock
(Note
1),
LVDS Transmitter
(2)
IOE supports SDR, DDR, or
Non-Registered Datapath
Figure 8–3
LVDS Clock Domain
Arria II GX Device Handbook, Volume 1
is a block diagram of the
OD
+
-
) controls, and can
Figure 8–4
tx_out
shows
8–7
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