EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 106
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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5–14
Arria II GX PLL Hardware Overview
Figure 5–10. Arria II GX PLL Block Diagram
Notes to
(1) There are seven PLL output counters in Arria II GX devices.
(2) This is the VCO post-scale counter
Arria II GX Device Handbook, Volume 1
Dedicated clock inputs
from adjacent PLL
GCLK/RCLK
Cascade input
Figure
pfdena
5–10:
1
4
Table 5–8. Arria II GX PLL Features (Part 2 of 2)
Figure 5–10
Arria II GX PLL.
You can drive the GCLK or RCLK clock input with an output from another PLL, a
pin-driven GCLK or RCLK, or through a clock control block, provided the clock
control block is fed by an output from another PLL or a pin driven dedicated GCLK or
RCLK. An internally-generated global signal or general purpose I/O (GPIO) pin
cannot drive the PLL.
Input clock switchover
Notes to
(1) PLL_5 and PLL_6 do not have dedicated clock outputs.
(2) The same PLL clock output drives three single-ended or three differential I/O pairs. This is only supported in
(3) This is applicable only if the input clock jitter is within the input jitter tolerance specifications.
(4) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For
inclk0
inclk1
PLL_1 and PLL_3 of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
degree increments, the Arria II GX device can shift all output frequencies in increments of at least 45°. Smaller
degree increments are possible depending on the frequency and C counter value.
Table
Switchover
K
Clock
Block
.
shows a simplified block diagram of the major components of the
5–8:
Feature
÷n
clkswitch
clkbad0
clkbad1
activeclock
PFD
Circuit
Lock
CP
Yes
locked
LF
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
VCO
8
no compensation mode
ZDB mode
LVDS Compensation mode
Source Synchronous, normal modes
÷2
(2)
To DPA block on
Right PLLs
Arria II GX PLLs
/2, /4
8
8
© July 2010 Altera Corporation
÷C0
÷C1
÷C2
÷C3
÷Cn
÷m
(1)
PLLs in Arria II GX Devices
Casade output
to adjacent PLL
External clock outputs
DIFFCLK network
GCLK/RCLK network
GCLKs
RCLKs
DIFFCLK from
Right PLLs
LOAD_EN from
Right PLLs
External
memory
interface DLL
External clock
outputs
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