EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 107
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
Figure 5–11. External Clock Outputs for Arria II GX PLLs
Notes to
(1) You can feed these clock output pins with any one of the C[6..0], and m counters.
(2) The PLL<#>_CLKOUT<#>p and PLL<#>_CLKOUT<#>n pins can be either single-ended or pseudo-differential clock outputs. The Arria II GX
(3) These external clock enable signals are available only when you use the ALTCLKCTRL megafunction.
© July 2010
PLL only routes single-ended I/Os to PLL<#>CLKOUT<#>p pins, while you can use PLL<#>_CLKOUT<#>n pins as user I/Os.
Figure
Altera Corporation
f
5–11:
Arria II GX
PLLs
PLL Clock I/O Pins
Each PLL supports one of the following clock I/O pin configurations:
■
■
Figure 5–11
Any of the output counters (C[6..0]) or the M counter can feed the dedicated
external clock outputs, as shown in
can drive all the output pins available from a given PLL.
Each pin of a single-ended output pair can either be in-phase or 180° out-of-phase.
The Quartus II software places the NOT gate in your design into the IOE to
implement a 180° phase with respect to the other pin in the pair. The clock output pin
pairs support the same I/O standards as standard output pins, as well as LVDS_E_3R,
LVPECL, differential high-speed transceiver logic (HSTL), and differential SSTL.
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the
PLL<#>_CLKOUT<#>p (1), (2)
One single-ended I/O or one differential I/O pair.
Three single-ended I/O or three differential I/O pairs (this is only supported in
PLL_1 and PLL_3 of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260
devices). You can only access one differential I/O pair or one single-ended pin at a
time.
clkena0 (3)
C0
C1
C2
C3
C4
C5
C6
m
shows the clock I/O pins associated with Arria II GX PLLs.
I/O Features in Arria II GX Devices
clkena1 (3)
PLL<#>_CLKOUT<#>n (1), (2)
Figure
5–11. Therefore, one counter or frequency
Internal Logic
chapter.
Arria II GX Device Handbook, Volume 1
5–15
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