EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 213
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Pin Placement Guidelines
Guidelines for DPA-Disabled Differential Channels
© July 2010
Altera Corporation
When you use DPA-disabled channels, you must adhere to the guidelines in the
following sections.
DPA-Disabled Channel Driving Distance
Each PLL can drive all the DPA-disabled channels in the entire bank.
Using Corner and Center PLLs
You can use a corner PLL to drive all transmitter channels and you can use a center
PLL to drive all DPA-disabled receiver channels in the same I/O bank. In other
words, you can drive a transmitter channel and a receiver channel in the same LAB
row by two different PLLs, as shown in
A corner PLL and a center PLL can drive duplex channels in the same I/O bank, as
long as the channels driven by each PLL are not interleaved. No separation is
necessary between the group of channels driven by the corner and center PLLs. Refer
to
Figure 8–25
and
Figure
8–26.
Figure
8–25.
Arria II GX Device Handbook, Volume 1
8–29
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