EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 20
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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1–6
Arria II Device Architecture
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Arria II devices include a customer-defined feature set optimized for cost-sensitive
applications and offer a wide range of density, memory, embedded multiplier, I/O,
and packaging options. Arria II devices support external memory interfaces and I/O
protocols required by wireless, wireline, broadcast, computer, storage, and military
markets. They inherit the 8-input ALM, M9K and M144K embedded RAM block, and
high-performance DSP blocks from the Stratix
cost-optimized I/O cell and a transceiver optimized for 6.375 Gbps speeds.
Figure 1–1
architecture, respectively.
Figure 1–1. Architecture Overview for Arria II GX Devices
Transceiver
PLL
Blocks
and
PLL
DLL
Figure 1–2
High-Speed Differential I/O,
High-Speed Differential I/O,
General Purpose I/O, and
General Purpose I/O, and
Plug and Play PCIe hard IP
All the blocks in this graphic are for the largest density in the
× ×
Memory Interface
Arria II GX family. The number of blocks can vary based on
Memory Interface
1, 2, ×4, and ×8
show an overview of the Arria II GX and Arria II GZ device
Embedded Memory, Clock Networks)
the density of the device.
(Logic Elements, DSP,
Arria II GX FPGA Fabric
®
High-Speed Differential I/O,
High-Speed Differential I/O,
General Purpose I/O, and
General Purpose I/O, and
IV device family with a
Chapter 1: Overview for the Arria II Device Family
Memory Interface
Memory Interface
December 2010 Altera Corporation
Arria II Device Architecture
Differential I/O
Differential I/O
High-Speed
High-Speed
DLL
with DPA,
Purpose
Interface
with DPA,
Purpose
General
I/O, and
Memory
Interface
General
Memory
I/O, and
PLL
PLL
PLL
PLL
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