EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 631
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Table 1–34. Transceiver Specifications for Arria II GX Devices (Part 7 of 7)
Digital reset
pulse width
Notes to
(1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Ensure that input specifications are not violated during this period.
(2) The device cannot tolerate prolonged operation at this absolute maximum.
(3) You must use the 1.1-V RX V
(4) The rate matcher supports only up to ±300 parts per million (ppm).
(5) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to
(6) The time in which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to
(7) The time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to
(8) The time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to
(9) The rise/fall time is specified from 20% to 80%.
(10) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is
(11) If your design uses more than one dynamic reconfiguration controller instances (altgx_reconfig) to control the transceiver channels (altgx) physically located on the same side of the device, and if
Description
configured in Receiver only or Receiver and Transmitter mode. For more information, refer to
you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum
specification listed.
Symbol/
Table
1–34:
Condition
—
ICM
setting if the input serial data standard is LVDS and the link is DC-coupled.
Min
I3
Typ
Max
Min
(Note 1)
Figure
Typ
1–1.
AN 558: Implementing Dynamic Reconfiguration in Arria II
C4
Minimum is 2 parallel clock cycles
Max
Figure
Figure
1–1.
1–2.
Min
C5 and I5
Typ
Max
Devices.
Min
Figure
Typ
C6
1–1.
Max
Unit
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