EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 249
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX45DF29I5N PDF datasheet #6
- Current page: 249 of 692
- Download datasheet (22Mb)
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Transmitter
Figure 8–5. Serializer Bypass Path
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width to the IOE is 1 and 2 bits, respectively.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
Figure 8–6. LVDS Transmitter in Clock Output Mode
Note to
(1) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
December 2010 Altera Corporation
Figure
Figure
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
8–6:
8–5:
tx_coreclock
Differential applications often require specific clock-to-data alignments or a specific
data rate to clock rate factors. You can configure any Arria II LVDS transmitter to
generate a source-synchronous transmitter clock output. This flexibility allows the
placement of the output clock near the data outputs to simplify board layout and
reduce clock-to-data skew. The output clock can also be divided by a factor of 1, 2, 4, 6,
8, or 10, depending on the serialization factor. The phase of the clock in relation to the
data can be set at 0° or 180° (edge or center aligned). The PLLs provide additional
support for other phase shifts in 45° increments. These settings are made statically in
the Quartus II MegaWizard
Figure 8–6
mode, you can use an LVDS data channel as a clock output channel.
FPGA
Fabric
FPGA
Fabric
tx_in 10
shows the Arria II LVDS transmitter in clock output mode. In clock output
(Note
1), (2),
DIN
Serializer
PLL (4)
PLL
(1)
3
DOUT
Parallel
Transmitter Circuit
(3)
LVDS_LOAD_EN
2
diffioclk
™
Plug-In Manager software.
IOE
Series
tx_inclock
Arria II Device Handbook Volume 1: Device Interfaces and Integration
LVDS Transmitter
IOE supports SDR, DDR, or
Non-Registered Datapath
LVDS Clock Domain
txclkout+
txclkout–
+
-
tx_out
8–9
Related parts for EP2AGX45DF29I5N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: