EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 444
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Price
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Manufacturer:
ALTERA
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Manufacturer:
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1–58
Arria II Device Handbook Volume 2: Transceivers
1
Figure 1–56
Figure 1–56. 1000 Base-X PHY in a GIGE OSI Reference Model
In GIGE functional mode, Arria II GX and GZ devices have built-in circuitry to
support the following PCS and PMA functions defined in the IEEE 802.3 specification:
■
■
■
■
■
Arria II GX and GZ transceivers do not have built-in support for some PCS functions;
for example, auto-negotiation state machine, collision-detect, and carrier-sense. If
required, you must implement these functions in a PLD logic array or external
circuits.
8B/10B encoding and decoding
Synchronization
Upstream transmitter and local receiver clock frequency compensation (rate
matching)
Clock recovery from the encoded data forwarded by the receiver PMD
Serialization and deserialization
shows the 1000 Base-X PHY position in a GIGE OSI reference model.
OSI Reference
Model Layers
Presentation
Application
Transport
Data Link
Network
Physical
Session
LAN CSMA/DC Layers
MAC (Optional)
Chapter 1: Transceiver Architecture in Arria II Devices
Reconcilation
Higher Layers
Medium
PMD
MAC
PCS
PMA
LLC
GMII
1000 Base-X PHY
December 2010 Altera Corporation
Functional Modes
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