EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 527
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
Because all 16 channels are identical, using a single tx_clkout to clock the transmitter
phase compensation FIFO in all 16 channels results in only one global or regional
clock resource being used instead of four. To implement this clocking scheme, you
must choose the transmitter phase compensation FIFO write clocks instead of the
Quartus II software automatic selection, as described in
Phase Compensation FIFO Write
User-Selected Transmitter Phase Compensation FIFO Write Clock
The ALTGX MegaWizard Plug-In Manager provides an optional tx_coreclk port for
each instantiated transmitter channel. If you enable this port, the Quartus II software
does not automatically select the transmitter phase compensation FIFO write clock
source. Instead, the signal that you drive on the tx_coreclk port of the channel clocks
the write side of its transmitter phase compensation FIFO.
Use the flexibility of selecting the transmitter phase compensation FIFO write clock to
reduce clock resource utilization (global, regional, or both). You can connect the
tx_coreclk ports of all identical channels in your design and drive them using a
common clock driver that has 0 PPM frequency difference with respect to the FIFO
read clocks of all your channels. Use the common clock driver to clock the transmitter
data and control logic in the FPGA fabric for all identical channels. This FPGA
fabric-transceiver interface clocking scheme uses only one global or regional clock
resource for all identical channels in your design.
Clock”.
Arria II Device Handbook Volume 2: Transceivers
“User-Selected Transmitter
2–37
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