EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 581
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 4: Reset Control and Power Down in Arria II Devices
Transceiver Reset Sequences
Figure 4–3. Sample Reset Sequence for Four Transmitter Only Channels
December 2010 Altera Corporation
Reset and Power-Down Signals
Ouput Status Signals
pll_powerdown
Transmitter Only Channel
This configuration contains only a transmitter channel. If you create a Transmitter
Only instance in the ALTGX MegaWizard Plug-In Manager in Basic ×4 functional
mode, use the reset sequence shown in
tx_digitalreset
As shown in
Transmitter Only channel configuration:
1. After power up, assert pll_powerdown for a minimum period of 1s (the time
2. Keep the tx_digitalreset signal asserted during this time period. After you
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
pll_locked
between markers 1 and 2).
de-assert the pll_powerdown signal, the transmitter PLL starts locking to the
transmitter input reference clock.
(marker 3), de-assert the tx_digitalreset signal (marker 4). The transmitter is
ready to transmit data.
1
Figure
1 μs
4–3, perform the following reset sequence steps for the
2
3
4
Figure
4–3.
Arria II Device Handbook Volume 2: Transceivers
4–7
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