EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 182
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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6–24
Arria II Device Handbook Volume 1: Device Interfaces and Integration
The R
external 50- Ω ±1% resistors connected to the RUP and RDN pins and dynamically
enables or disables the transistors until they match. Calibration occurs at the end of
device configuration. When the calibration circuit finds the correct impedance, it
powers down and stops changing the characteristics of the drivers.
I/O standards that support R
Table 6–13. Selectable I/O Standards with R
Dynamic R
Arria II GZ devices support on and off dynamic termination, both series and parallel,
for a bidirectional I/O in all I/O banks.
supported in Arria II GZ devices. Dynamic parallel termination is enabled only when
the bidirectional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bidirectional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bidirectional path because signal integrity is
optimized depending on the direction of the data.
SSTL-2 Class I, II
SSTL-18 Class I, II
SSTL-15 Class I, II
HSTL-18 Class I, II
HSTL-15 Class I, II
HSTL-12 Class I, II
Differential SSTL-2 Class I, II
Differential SSTL-18 Class I, II
Differential SSTL-15 Class I, II
Differential HSTL-18 Class I, II
Differential HSTL-15 Class I, II
Differential HSTL-12 Class I, II
T
OCT calibration circuit compares the total impedance of the I/O buffer to the
I/O Standard
S
and R
T
OCT for Single-Ended I/O Standard for Arria II GZ Devices
T
OCT with calibration.
(Column I/O) (Ω)
T
R
Figure 6–9
OCT with Calibration for Arria II GZ Devices
T
OCT Setting
50
50
50
50
50
50
50
50
50
50
50
50
shows the termination schemes
Chapter 6: I/O Features in Arria II Devices
December 2010 Altera Corporation
R
Table 6–13
(Row I/O) (Ω)
T
OCT Setting
50
50
50
50
50
50
50
50
50
50
50
50
OCT Support
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