EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 624
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
ALTERA
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1–20
Table 1–33. Differential I/O Standard Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
2.5 V
LVDS
(HIO)
2.5 V
LVDS
(VIO)
RSDS
(HIO)
RSDS
(VIO)
Mini-LVDS
(HIO)
Mini-LVDS
(VIO)
LVPECL
Notes to
(1) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(2) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in
(3) R
(4) For D
Standard
I/O
(1)
0.45 V; the maximum input voltage is 1.95 V.
L
range: 90
Table
MAX
Power Consumption for the Arria II Device Family
> 700 Mbps, the minimum input voltage is 0.85 V; the maximum input voltage is 1.75 V. For F
2.375
2.375
2.375
2.375
2.375
2.375
2.375
2.375
Min
1–33:
RL
V
CCIO
Typ
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Table 1–33
Altera offers two ways to estimate power for a design:
■
■
The interactive Microsoft Excel-based Early Power Estimator is typically used prior to
designing the FPGA in order to get a magnitude estimate of the device power. The
Quartus II PowerPlay Power Analyzer provides better quality estimates based on the
specifics of the design after place-and-route is complete. The PowerPlay Power
Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities which, when combined with detailed circuit models, can yield very
accurate power estimates.
110 .
(V)
Using the Microsoft Excel-based Early Power Estimator
Using the Quartus
2.625
2.625
2.625
2.625
2.625
2.625
2.625
2.625
Max
lists the differential I/O standard specifications for Arria II GZ devices.
Min
100
100
100
100
200
200
300
300
V
1.25 V
1.25 V
1.25 V
1.25 V
TH
Cond.
V
V
V
V
CM
CM
CM
CM
—
—
—
—
(mV)
=
=
=
=
®
II PowerPlay Power Analyzer feature
Max
600
600
—
—
—
—
—
—
—
—
0.05
1.05
0.05
1.05
Min
0.3
0.3
0.4
0.4
0.6
1
V
700 Mbps
700 Mbps
700 Mbps
700 Mbps
700 Mbps
700 Mbps
Condition Max
“Transceiver Performance Specifications” on page
ICM(DC)
D
D
D
D
D
D
MAX
MAX
MAX
MAX
MAX
MAX
—
—
—
—
>
>
>
(V)
(Note 2)
1.55 0.247
1.55 0.247
1.32
1.32
1.8
1.8
1.4
1.4
1.8
1.6
(4)
(4)
5
5
Chapter 1: Device Datasheet for Arria II Devices
0.247
0.247
0.25
0.25
Min
0.1
0.1
—
—
MAX
V
OD
December 2010 Altera Corporation
(V)
Typ
0.2
0.2
—
—
—
—
—
—
—
—
700 Mbps, the minimum input voltage is
(3)
Max
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
—
—
Electrical Characteristics
1.125
1.125
Min
0.5
0.5
—
—
1–21.
1
1
1
1
V
OS
1.25
1.25
1.25
1.25
Typ
1.2
1.2
1.2
1.2
(V)
—
—
(3)
1.375
1.375
Max
1.5
1.4
1.5
1.5
1.4
1.5
—
—
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