EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 572
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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EP2AGX45DF29I5N
Manufacturer:
ALTERA
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EP2AGX45DF29I5N
Manufacturer:
ALTERA
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3–14
Arria II Device Handbook Volume 2: Transceivers
1
Figure 3–5
Figure 3–5. Transceiver Channel Instances before Compilation for Example 4
Figure 3–6
Figure 3–6. Combined Transceiver Instances after Compilation for Example 4
You can force the placement of the transceiver channels in specific transceiver banks
by assigning pins to the tx_dataout and rx_datain ports of inst0 and inst1.
Ch1 of inst0
Effective Data Rate: 3.125 Gbps
Ch0 of inst0
Effective Data Rate: 3.125 Gbps
Effective Data Rate: 3.125 Gbps
Ch3 of inst0
Effective Data Rate: 3.125 Gbps
Ch2 of inst0
shows the transceiver instances before compilation for Example 4.
shows the transceiver instances after compilation for Example 4.
Transceiver Block 0
Base Data Rate:
3.125 Gbps
CMU PLL
Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
Effective Data Rate: 3.125 Gbps
Input Clock Frequency: 156.125 MHz
Number of Channels: 7
Effective Data Rate: 3.125 Gbps
Input Clock Frequency: 156.25 MHz
Number of Channels: 1
Inst0
Inst1
Combining Transceiver Instances in Multiple Transceiver Blocks
Effective Data Rate: 3.125 Gbps
Effective Data Rate: 3.125 Gbps
Ch5 of inst0
Ch4 of inst0
Ch0 of inst1
Effective Data Rate: 3.125 Gbps
Ch6 of inst0
Effective Data Rate: 3.125 Gbps
Transceiver Block 1
Base Data Rate:
3.125 Gbps
December 2010 Altera Corporation
CMU PLL
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