EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 471
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer:
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Chapter 1: Transceiver Architecture in Arria II Devices
Test Modes
Test Modes
Figure 1–81. Serial Loopback Datapath
December 2010 Altera Corporation
Fabric
FPGA
Serial Loopback
1
Arria II GX and GZ devices provide various loopback options, pattern generators, and
verifiers that allow you to ensure the working of different functional blocks in the
transceiver channel. These modes include:
■
■
■
■
■
If you generate a Transmitter-only or Receiver-only configuration and enable
loopback mode, you will have an extra port that you must connect to the transceiver’s
counterpart port. These ports are described in
list).
This option is available for all functional modes except PCIe mode.
the datapath for serial loopback.
The data from the FPGA fabric passes through the transmitter channel and loops back
to the receiver channel, bypassing the receiver input buffer. The received data is
available to the FPGA logic for verification. Using this option, you can check the
operation for all enabled PCS and PMA functional blocks in the transmitter and
receiver channels.
When you enable the serial loopback option, the ALTGX MegaWizard Plug-In
Manager provides the rx_seriallpbken port to dynamically enable serial loopback on
a channel-by-channel basis when the signal is asserted high.
Serial loopback
Reverse serial loopback
Reverse serial pre-CDR loopback
PCIe reverse parallel loopback
BIST and PRBS Modes
Compensation
wrclk
TX Phase
FIFO
rdclk
wrclk
Byte Serializer
Receiver Channel PCS
Transmitter Channel PCS
rdclk
8B/10B Encoder
Table 1–30 on page 1–98
Arria II Device Handbook Volume 2: Transceivers
Figure 1–81
(the PMA port
Transmitter Channel
Receiver Channel
Serial Loopback
PMA
PMA
shows
1–85
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