EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 172

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–14
Arria II Device Handbook Volume 1: Device Interfaces and Integration
High-Speed Differential I/O with DPA Support
Programmable Current Strength
f
Arria II devices have the following dedicated circuitry for high-speed differential I/O
support:
■
■
■
■
■
■
■
For more information about DPA support, refer to the
Interfaces with DPA in Arria II Devices
The output buffer for each Arria II I/O pin has a programmable current-strength
control for certain I/O standards. You can use programmable current strength to
mitigate the effects of high signal attenuation due to a long transmission line or a
legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have several
levels of current strength that you can control.
programmable current strength settings for Arria II devices.
Table 6–7. Programmable Current Strength for Arria II GX Devices (Part 1 of 2)
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment circuitry
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
(2)
(2)
I/O Standard
chapter.
Table 6–7
I
OL
for Top, Bottom, and Right I/O Pins
/ I
OH
Current Strength Setting (mA)
High-Speed Differential I/O
16, 12, 10, 8, 6, 4, 2
16, 12, 10, 8, 6, 4, 2
Chapter 6: I/O Features in Arria II Devices
and
12, 10, 8, 6, 4, 2
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
[12], 8, 4
December 2010 Altera Corporation
12, 10, 8
12, 10, 8
12, 10, 8
12, 10, 8
16, 12
Table 6–8
12, 8
[2]
16
16
16
list the
(Note 1)
I/O Structure