EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 107
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer:
ALTERA
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- EP2AGX45CU17C6N PDF datasheet
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Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Figure 5–1. GCLK Networks in Arria II GX Devices
Notes to
(1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(2) Because there are no dedicated clock pins on the left side of an Arria II GX device, GCLK[0..3] are not driven by any clock pins.
December 2010 Altera Corporation
Figure
Top Left PLL
Bottom Left PLL
Global Clock Networks
5–1:
Arria II devices provide up to 16 GCLKs that can drive throughout the device, serving
as low-skew clock sources for functional blocks such as adaptive logic modules
(ALMs), digital signal processing (DSP) blocks, embedded memory blocks, and PLLs.
Arria II I/O elements (IOEs) and internal logic can drive GCLKs to create internally
generated GCLKs and other high fan-out control signals; for example, synchronous or
asynchronous clears and clock enables.
PLLs that can drive GCLK networks in Arria II devices.
PLL_1
PLL_4
GCLK[0..3] ( 2 )
GCLK[12..15]
GCLK[4..7]
CLK[4..7]
CLK[12..15]
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure 5–1
GCLK[8..11]
and
Figure 5–2
PLL_2
PLL_5
PLL_6
PLL_3
Bottom Right PLL
(1)
(1)
show CLK pins and
Top Right PLL
Center PLLs
CLK[8..11]
5–3
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