EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 435
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 1: Transceiver Architecture in Arria II Devices
Calibration Block
December 2010 Altera Corporation
Figure 1–49
and cal_blk_powerdown ports in the ALTGX MegaWizard Plug-In Manager to control
the calibration block. Drive the cal_blk_clk port of all ALTGX instances that are
associated with the same calibration block from the same input pin or logic.
Figure 1–49. Input Signals to the Calibration Blocks
Notes to
(1) You must connect a separate 2 k (tolerance max ± 1%) external resistor on each RREF pin in the Arria II GX and GZ
(2) This is the input clock to the calibration block. You can use dedicated clock routes such as the global or regional clock;
(3) The calibration block restarts the calibration process following de-assertion of the cal_blk_powerdown status.
device to GND. To ensure proper operation of the calibration block, the RREF resistor connection in the board must
be free from external noise.
however, if you do not have a suitable input reference clock or dedicated clock routing resources available, use
divide-down logic from the FPGA fabric to generate a slow clock, local clocking routing, or both.
Drive this signal of all ALTGX instances that are associated with the same calibration block from the same input or
logic.
cal_blk_powerdown (3)
OCT Calibration Control
Figure
cal_blk_clk (2)
shows the calibration block diagram. You can instantiate the cal_blk_clk
1–49:
RREF pin (1)
OCT Calibration
Circuit
Calibration Block
Reference
Generator
Internal
Voltage
Calibration Circuit
Analog Block
Arria II Device Handbook Volume 2: Transceivers
Reference
Signal
Calibration Control
Analog Block
1–49
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