EP3C16Q240C8N Altera, EP3C16Q240C8N Datasheet - Page 96

• Manufacturer Part Number: EP3C16Q240C8N
• Description: IC CYCLONE III FPGA 16K 240PQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16Q240C8N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 160
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 92
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2458

5–32
Spread-Spectrum Clocking
PLL Specifications
Cyclone III Device Handbook, Volume 1
f
f
The phasestep signal is latched on the negative edge of scanclk. In
this is shown by the second scanclk falling edge. phasestep must stay high for at
least two scanclk cycles. On the second scanclk rising edge after phasestep is
latched (indicated by the fourth rising edge), the values of phaseupdown and
phasecounterselect are latched and the PLL starts dynamic phase shifting for the
specified counter or counters and in the indicated direction. On the fourth scanclk
rising edge, phasedone goes high to low and remains low until the PLL finishes
dynamic phase shifting. You can perform another dynamic phase shift after the
phasedone signal goes from low to high.
Depending on the VCO and scanclk frequencies, phasedone low time may be
greater than or less than one scanclk cycle. The maximum time for reconfiguring
phase shift dynamically is to be determined (TBD) based on device characterization.
After phasedone goes from low to high, you can perform another dynamic phase
shift. phasestep pulses must be at least one scanclk cycle apart.
For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer
to the
The Cyclone III device family can accept a spread-spectrum input with typical
modulation frequencies. However, the device cannot automatically detect that the
input is a spread-spectrum signal. Instead, the input signal looks like deterministic
jitter at the input of the PLL. Cyclone III device family PLLs can track a
spread-spectrum input clock as long as it is in the input jitter tolerance specifications
and the modulation frequency of the input clock is below the PLL bandwidth, which
is specified in the fitter report. The Cyclone III device family cannot generate
spread-spectrum signals internally.
For information about PLL specifications, refer to the
Cyclone III LS Device Data Sheet
ALTPLL_RECONFIG Megafunction User
chapters.
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Guide.
Cyclone III Device Data Sheet
© December 2009 Altera Corporation
Spread-Spectrum Clocking
Figure
5–24,
and