EP3C16Q240C8N Altera, EP3C16Q240C8N Datasheet - Page 57

• Manufacturer Part Number: EP3C16Q240C8N
• Description: IC CYCLONE III FPGA 16K 240PQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16Q240C8N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 160
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 92
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2458

Embedded Multiplier Block Overview
© December 2009
CIII51005-2.2
Altera Corporation
The Cyclone
combination of on-chip resources and external interfaces that help to increase
performance, reduce system cost, and lower the power consumption of digital signal
processing (DSP) systems. The Cyclone III device family, either alone or as DSP
device co-processors, are used to improve price-to-performance ratios of DSP
systems. Particular focus is placed on optimizing Cyclone III and Cyclone III LS
devices for applications that benefit from an abundance of parallel processing
resources, which include video and image processing, intermediate frequency (IF)
modems used in wireless communications systems, and multi-channel
communications and video systems.
This chapter contains the following sections:
■
■
■
Figure 4–1
array blocks (LABs). The embedded multiplier is configured as either one 18 × 18
multiplier or two 9 × 9 multipliers. For multiplications greater than 18 × 18, the
Quartus
are no restrictions on the data width of the multiplier, but the greater the data width,
the slower the multiplication process.
Figure 4–1. Embedded Multipliers Arranged in Columns with Adjacent LABs
“Embedded Multiplier Block Overview” on page 4–1
“Architecture” on page 4–3
“Operational Modes” on page 4–5
®
II software cascades multiple embedded multiplier blocks together. There
shows one of the embedded multiplier columns with the surrounding logic
®
III device family (Cyclone III and Cyclone III LS devices) includes a
1 LAB
Row
4. Embedded Multipliers in the
Embedded
Multiplier
Embedded
Multiplier
Column
Cyclone III Device Family
Cyclone III Device Handbook, Volume 1