EP3C16Q240C8N Altera, EP3C16Q240C8N Datasheet - Page 228

• Manufacturer Part Number: EP3C16Q240C8N
• Description: IC CYCLONE III FPGA 16K 240PQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16Q240C8N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 160
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 92
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2458

9–68
Table 9–21. Cyclone III Device Family Configuration Pin Summary (Part 2 of 2)
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 1 of 4)
Cyclone III Device Handbook, Volume 1
Notes to
(1) In Cyclone III devices, the CRC_ERROR pin is a dedicated output by default. Optionally, you can enable the CRC_ERROR pin as an open-drain
(2) AP configuration is for Cyclone III devices only.
MSEL [3..0]
nCONFIG
nSTATUS
Bank
5
5
Pin Name
output in the CRC Error Detection tab from the Device and Pin Options dialog box.
Table
DEV_OE
DEV_CLRn
9–21:
Description
Mode
User
N/A
N/A
N/A
Table 9–22
your board for successful configuration. Some of these pins may not be required for
your configuration scheme.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration
Scheme
lists the dedicated configuration pins that must be connected properly on
All
All
All
Input/Output
Input
Input
Bidirectional
open-drain
Pin Type
Input
Input
Dedicated
—
—
4-bit configuration input that sets the Cyclone III device
family configuration scheme. These pins must be hardwired
to V
pull-down resistors that are always active.
Some of the smaller devices or package options of
Cyclone III devices do not have the MSEL[3] pin; therefore,
the AP configuration scheme is not supported.
Configuration control input. Pulling this pin low with external
circuitry during user mode causes the Cyclone III device
family to lose its configuration data, enter a reset state, and
tri-state all I/O pins. Returning this pin to a logic-high level
starts a reconfiguration.
The Cyclone III device family drives nSTATUS low
immediately after power-up and releases it after the POR
time.
■
■
Driving nSTATUS low after configuration and initialization
does not affect the configured device. If you use a
configuration device, driving nSTATUS low causes the
configuration device to attempt to configure the device, but
because the device ignores transitions on nSTATUS in user
mode, the device does not reconfigure. To start a
reconfiguration, nCONFIG must be pulled low.
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source (for example, another
Cyclone III device family) drives the nSTATUS pin low
during configuration or initialization, the target device
enters an error state.
C CA
or GND. The MSEL[3..0] pins have internal 9-kΩ
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V
V
CC IO
CC IO
Description
© December 2009 Altera Corporation
Configuration Mode
Optional, AP
Optional, AP
Configuration Features
(2)
(2)