EP3C16Q240C8N Altera, EP3C16Q240C8N Datasheet - Page 200

• Manufacturer Part Number: EP3C16Q240C8N
• Description: IC CYCLONE III FPGA 16K 240PQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16Q240C8N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 160
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 92
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2458

9–40
Table 9–13. PS Configuration Timing Parameters for Cyclone III Device Family
Cyclone III Device Handbook, Volume 1
f
t
t
t
Notes to
(1) This information is preliminary.
(2) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting the device.
(4) Cyclone III devices can support a DCLK f
(5) For more information about the initialization clock cycles required in Cyclone III device family, refer to
Symbol
M AX
CD2UM
CD2C U
CD2UM C
Table
DCLK frequency
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option
on
9–13:
PS Configuration Using a Download Cable
In this section, the generic term "download cable" includes the Altera USB-Blaster
universal serial bus (USB) port download cable, MasterBlaster™ serial/USB
communications cable, ByteBlaster II parallel port download cable, the
ByteBlasterMV™ parallel port download cable, and the Ethernet-Blaster
communications cable.
In the PS configuration with a download cable, an intelligent host (such as a PC)
transfers data from a storage device to the device using the download cable.
The programming hardware or download cable then places the configuration data
one bit at a time on the DATA[0] pin of the device. The configuration data is clocked
into the target device until CONF_DONE goes high. The CONF_DONE pin must have an
external 10-kΩ pull-up resistor for the device to initialize.
When you use a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs. Additionally, the
Enable user-supplied start-up clock (CLKUSR) option has no effect on the device
initialization because this option is disabled in the .sof when programming the device
using the Quartus II programmer and download cable. Therefore, if you turn on the
CLKUSR option, you do not need to provide a clock on CLKUSR when you are
configuring the device with the Quartus II programmer and a download cable.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Parameter
MAX
of 133 MHz. Cyclone III LS devices can support a DCLK f
(3)
4 × maximum DCLK period
t
cycles × CLKUSR period)
CD2CU
+ (initialization clock
(Note 1)
Minimum
300
—
(Part 2 of 2)
Table 9–5 on page
MAX
© December 2009 Altera Corporation
of 100 MHz.
(5)
Maximum
100
Configuration Features
9–10.
650
—
—
(4)
MHz
Unit
μs
—
—