XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 92

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

XC4000 Series Field Programmable Gate Arrays
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1:
Note 2:
Note 3:
XC4000L Switching Characteristics
XC4000L timing parameters were not available at the time this document was released. See the Xilinx W
http://www.xilinx.com for the latest available information.
XC4000EX Switching Characteristics
XC4000EX timing parameters were not available at the time this document was released. See the Xilinx W
http://www.xilinx.com for the latest available information.
XC4000XL Switching Characteristics
XC4000XL timing parameters were not available at the time this document was released. See the Xilinx W
http://www.xilinx.com for the latest available information.
4-96
Setup and Hold
Input (TDI) to clock (TCK)
Input (TDI) to clock (TCK)
Input (TMS) to clock (TCK)
Input (TMS) to clock (TCK)
Propagation Delay
Clock (TCK) to Pad (TDO)
Clock
Clock (TCK) High
Clock (TCK) Low
Power-On Reset
JTAG operation after valid
setup time
hold time
setup time
hold time
Vcc
Description
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Speed Grade
T
T
Symbol
T
T
T
T
T
TMSTCK
TCKTMS
T
TDITCK
TCKTDI
TCKPO
RJTAG
TCKH
TCKL
Min
-4
Max
Min
-3
Max
Min
Preliminary
September 18, 1996 (Version 1.04)
-2
Max
EB
EB
EB
LINX at
LINX at
LINX at