XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 89

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

XC4000E IOB Input Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1:
Note 2:
Note 3:
September 18, 1996 (Version 1.04)
Setup Times (TTL Inputs)
Pad to Clock (IK),
(CMOS Inputs)
Pad to Clock (IK),
(TTL or CMOS)
Clock Enable (EC) to Clock
(IK), no delay
Global Set/Reset (Note 3)
Delay from GSR net
GSR width
GSR inactive to first active
through Q to I1, I2
Clock (IK) edge
with delay
Description
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
no delay
with delay
no delay
with delay
Speed Grade
Symbol
T
T
T
T
T
T
PICKDC
T
T
T
PICKD
PICKC
ECIKD
MRW
PICK
ECIK
RRI
MRI
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
All devices
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Device
10.9
10.9
10.9
11.1
11.3
11.8
14.0
14.0
12.0
12.0
12.3
12.8
13.0
13.5
16.0
16.0
10.4
10.4
10.4
10.4
10.7
11.1
14.0
14.0
13.0
Min
4.0
6.0
3.5
-4
Max
12.0
10.2
11.4
11.4
10.3
10.5
10.9
12.1
12.1
10.1
11.3
11.3
11.5
Min
2.6
8.2
8.7
9.2
9.6
9.8
3.3
8.8
9.7
9.9
2.5
8.1
8.5
9.1
9.5
9.7
-3
Max
7.8
10.0
10.0
12.1
12.1
10.6
11.0
11.5
Min
Preliminary
2.0
6.0
6.1
6.2
6.3
6.4
7.9
9.4
2.4
6.9
8.0
8.1
8.2
8.3
2.1
4.3
5.6
6.7
6.9
7.1
9.0
-2
Max
6.8
4-93