XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 5

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

Global Signal Access to Logic
There is additional access from global clocks to the F and G
function generator inputs.
Configuration Pin Pull-Up Resistors
During configuration, the three mode pins, M0, M1, and
M2, have weak pull-up resistors. For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be
left unconnected.
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configu-
ration.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up
Like the XC3000A, XC4000-Series devices have “Soft
Start-up.” When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids poten-
tial ground bounce when all outputs are turned on simulta-
neously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
XC4000 and XC4000A Compatibility
Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recom-
piled for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.
Additional Improvements in XC4000EX
Only
Increased Routing
New interconnect in the XC4000EX includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve
“Quad Lines” in each CLB row and column include optional
repowering buffers for maximum speed. Additional high-
performance routing near the IOBs enhances pin flexibility.
September 18, 1996 (Version 1.04)
Faster Input and Output
A fast, dedicated early clock sourced by global clock buffers
is available for the IOBs. To ensure synchronization with
the regular global clocks, a Fast Capture latch driven by the
early clock is available. The input data can be initially
loaded into the Fast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See
nals” on page 24
Latch Capability in CLBs
Storage elements in the XC4000EX CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
IOB Output MUX From Output Clock
A multiplexer in the IOB allows the output clock to select
either the output data or the IOB clock enable as the output
to the pad. Thus, two different data signals can share a sin-
gle output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive pack-
age. This multiplexer can also be configured as an AND-
gate to implement a very fast pin-to-pin path. See
Output Signals” on page 27
Express Configuration Mode
A new slave configuration mode accepts parallel data input.
Data is processed in parallel, rather than serialized inter-
nally. Therefore, the data rate is eight times that of the six
conventional configuration modes.
Additional Address Bits
Larger devices require more bits of configuration data. A
daisy chain of several large XC4000EX devices may
require a PROM that cannot be addressed by the eighteen
address bits supported in the XC4000E. The XC4000EX
family therefore extends the addressing in Master Parallel
configuration mode to 22 bits.
for more information.
for more information.
“IOB Input Sig-
“IOB
4-9