XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 25

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

The user can specify that the IOB function generator be
used, by placing special library symbols beginning with the
letter “O.” For example, a 2-input AND-gate in the IOB func-
tion generator is called OAND2. Use the symbol input pin
labelled “F” for the signal on the critical path. This signal is
placed on the OK pin — the IOB input with the shortest
delay to the function generator. Two examples are shown in
Figure
Other IOB Options
There are a number of other programmable options in the
XC4000-Series IOB.
Pull-up and Pull-down Resistors
Programmable pull-up and pull-down resistors are useful
for tying unused pins to Vcc or Ground to minimize power
consumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to Vcc.
The configurable pull-down resistor is an n-channel transis-
tor that pulls to Ground.
The value of these resistors is 50 k
value makes them unsuitable as wired-AND pull-up resis-
tors.
The pull-up resistors for most user-programmable IOBs are
active during the configuration process. See
page 78
ing configuration.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis-
tor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal pull-
up, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
Independent Clocks
Separate clock signals are provided for the input and output
flip-flops. The clock can be independently inverted for each
flip-flop within the IOB, generating either falling-edge or ris-
ing-edge triggered flip-flops. The clock inputs for each IOB
September 18, 1996 (Version 1.04)
Figure 21: Output AND and MUX Symbols in
XC4000EX IOB
21.
for a list of pins with pull-ups active before and dur-
OAND2
F
X6598
D0
D1
S0
100 k . This high
OMUX2
Table 24 on
X6599
O
are independent, except that in the XC4000EX, the Fast
Capture latch shares an IOB input with the output clock pin.
Early Clock for IOBs (XC4000EX only)
Special early clocks are available for IOBs. These clocks
are sourced by the same sources as the Global Low-Skew
buffers, but are separately buffered. They have fewer loads
and therefore less delay. The early clock can drive either
the IOB output clock or the IOB input clock, or both. The
early clock allows fast capture of input data, and fast clock-
to-output on output data. The Global Early buffers that
drive these clocks are described in
ers (XC4000EX only)” on page
Fast Clock for IOBs (XC4000EX only)
Very fast clocks driven by FastCLK buffers are also avail-
able for IOBs. These clocks are sourced by semi-dedicated
pads—the pads can be used as general I/O if not used to
drive FastCLK buffers. There are two FastCLK buffers on
the left edge, and two on the right edge of the device. They
provide the fastest method of reaching the IOB clock pins.
The FastCLK buffer can drive either the IOB output clock or
the IOB input clock, or both. These buffers allow the fastest
possible setup times and clock-to-output times. The Fast-
CLK buffers are described in
(XC4000EX only)” on page
Global Set/Reset
As with the CLB registers, the Global Set/Reset signal
(GSR) can be used to set or clear the input and output reg-
isters, depending on the value of the INIT attribute or prop-
erty. The two flip-flops can be individually configured to set
or clear on reset and after configuration. Other than the
global GSR net, no user-controlled set/reset signal is avail-
able to the I/O flip-flops. The choice of set or clear applies
to both the initial state of the flip-flop and the response to
the Global Set/Reset pulse. See
page 13
JTAG Support
Embedded logic attached to the IOBs contains test struc-
tures compatible with IEEE Standard 1149.1 for boundary
scan testing, permitting easy chip and board-level testing.
More information is provided in
page
Three-State Buffers
A pair of 3-state buffers is associated with each CLB in the
array. (See
can be used to drive signals onto the nearest horizontal
longlines above and below the CLB. They can therefore be
used to implement multiplexed or bidirectional buses on the
horizontal longlines, saving logic resources. Programma-
ble pull-up resistors attached to these longlines help to
implement a wide wired-AND function.
50.
for a description of how to use GSR.
Figure 27 on page
43.
43.
34.) These 3-state buffers
“Global Nets and Buffers
“Global Nets and Buff-
“Global Set/Reset” on
“Boundary Scan” on
4-29