XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 82

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

XC4000 Series Field Programmable Gate Arrays
XC4000E CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1:
Note 2:
4-86
Hold Time after Clock K
F/G inputs
F/G inputs via H’
C inputs via H0 through H’
C inputs via H1 through H’
C inputs via H2 through H’
C inputs via DIN
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R,
Master Set/Reset (Note 1)
Width (High or Low)
Delay from Global Set/Reset net to Q
Global Set/Reset inactive to first
Toggle Frequency
going High to Q
active clock K edge
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
Export Control Max. flip-flop toggle rate.
Description
2
(MHz) (Note 2)
Speed Grade
Symbol
T
T
T
T
T
T
T
T
T
T
T
F
CKHH0
CKHH1
CKHH2
T
T
T
CKEC
T
MRW
CKIH
CKDI
RPW
MRQ
CKR
MRK
TOG
CKI
RIO
CH
CL
13.0
Min
4.5
4.5
5.5
0
0
0
0
0
0
0
0
-4
Max
23.0
113
6.5
11.5
Min
4.0
4.0
4.0
0
0
0
0
0
0
0
0
-3
Max
18.7
142
4.0
September 18, 1996 (Version 1.04)
11.5
Min
Preliminary
4.0
4.0
4.0
0
0
0
0
0
0
0
0
-2
Max
17.4
160
4.0