XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 42

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

XC4000 Series Field Programmable Gate Arrays
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in
Ground lines supplies the interior logic of the device.
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.
Typically, a 0.1 F capacitor connected near the Vcc and
Ground pins of the package will provide adequate decou-
pling.
Output buffers capable of driving/sinking the specified 12
mA (XC4000E) or 24 mA (XC4000EX) loads under speci-
fied worst-case conditions may be capable of driving/sink-
ing up to 10 times as much current under best case
conditions.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default) which
should be used where output rise and fall times are not
speed-critical.
4-46
Figure 41: XC4000-Series Power Distribution
Vcc
Figure
41. An independent matrix of Vcc and
GND
GND
Vcc
Logic
Power Grid
Ground and
Vcc Ring for
I/O Drivers
X5422
Pin Descriptions
There are three types of pins in the XC4000-Series
devices:
• Permanently dedicated pins
• User I/O pins that can have special functions
• Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with a 50 k
pull-up resistor.
After configuration, if an IOB is unused it is configured as
an input with a 50 k - 100 k pull-up resistor.
XC4000-Series devices have no dedicated Reset input.
Any user I/O can be configured to drive the Global Set/
Reset net, GSR. See
more information on GSR.
XC4000-Series devices have no Powerdown control input,
as the XC3000 and XC2000 families do. The XC3000/
XC2000 Powerdown control also 3-stated all of the device I/
O pins. For XC4000-Series devices, use the global 3-state
net, GTS, instead. This net 3-states all outputs, but does
not place the device in low-power mode. See
Signals” on page 27
Device pins for XC4000-Series devices are described in
Table
seven configuration modes are summarized in
page
78, in the “Configuration Timing” section.
18. Pin functions during configuration for each of the
for more information on GTS.
September 18, 1996 (Version 1.04)
“Global Set/Reset” on page 13
“IOB Output
Table 24 on
- 100 k
for