XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 84

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

XC4000 Series Field Programmable Gate Arrays
XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic
Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note:
4-88
Write Operation
Address write cycle time
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
(clock K period)
Applicable Read timing specifications are identical to16x2 Level-Sensitive Read timing.
Description
DATA OUT
ADDRESS
WCLK (K)
DATA IN
WE
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
Size Symbol
Speed Grade
T
T
T
T
T
T
T
T
T
WODS
WCDS
WPDS
WSDS
WHDS
DHDS
ASDS
AHDS
DSDS
T
ILO
T
15.0
Min
T
T
7.5
2.8
2.2
2.2
0.3
WSDS
0
0
DSDS
ASDS
-4
T
WODS
1 ms
Max
10.0
OLD
T
T
T
WHDS
AHDS
DHDS
14.4
Min
7.2
2.5
1.9
2.0
0
0
0
T
WPDS
-3
NEW
T
1 ms
Max
7.8
ILO
September 18, 1996 (Version 1.04)
X6474
11.6
Min
Preliminary
5.8
2.1
1.6
1.6
0
0
0
-2
1 ms
Max
7.0