XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 8

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

XC4000 Series Field Programmable Gate Arrays
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in
Latches (XC4000EX only)
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs.
described in
4-12
Figure 1: Simplified Block Diagram of XC4000-Series CLB (RAM and Carry Logic functions not shown)
C 1 • • • C 4
G 4
G 3
G 2
G 1
F 4
F 3
F 2
F 1
K
(CLOCK)
Table
FUNCTION
FUNCTION
LOGIC
LOGIC
G1-G4
4.
F1-F4
OF
OF
4
Storage element functionality is
G'
F'
Table
4.
H 1
FUNCTION
LOGIC
F', G',
AND
OF
H1
H'
DIN
F'
G'
H'
G'
H'
H'
F'
DIN
F'
G'
H'
D IN /H 2
Table 4: CLB Storage Element Functionality
(active rising edge is shown)
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
Legend:
Power-Up or
Flip-Flop
Latch
GSR
Mode
Both
__/
SR
0*
1*
SR/H 0
X
Multiplexer Controlled
by Configuration Program
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
EC
1
1
__/
X
X
X
CONTROL
CONTROL
0
1
0
K
S/R
S/R
September 18, 1996 (Version 1.04)
1*
1*
1*
EC
X
X
X
0
D
EC
D
EC
SD
RD
SD
RD
0*
0*
0*
0*
0*
SR
X
1
Q
Q
Bypass
Bypass
X
X
D
X
X
D
X
D
X6692
Y
X
YQ
XQ
SR
SR
D
Q
Q
D
Q
Q