XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 88

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

XC4000 Series Field Programmable Gate Arrays
XC4000E IOB Input Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1:
Note 2:
4-92
Propagation Delays
(TTL Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent
(CMOS Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent
(TTL or CMOS)
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2
Hold Times (Note 1)
Pad to Clock (IK), no delay
Clock Enable (EC) to Clock (IK),
latch, no delay
latch, no delay
(latch enable, active Low)
no delay
with delay
with delay
Description
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
with delay
with delay
T
T
T
T
T
Symbol
T
T
PID
PLI
PDLI
IKRI
IKLI
T
T
T
T
T
PDLIC
IKECD
IKPID
PIDC
IKEC
PLIC
IKPI
Speed Grade
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Device
Min
1.5
0
0
0
-4
Max
10.4
10.8
10.8
10.8
11.0
11.4
13.8
13.8
16.5
16.5
16.8
17.3
17.5
18.0
20.8
20.8
3.0
4.8
5.5
8.8
5.6
6.2
Min
1.5
0
0
0
-3
Max
10.2
10.6
10.8
11.2
12.4
13.7
12.4
13.2
13.4
13.8
14.0
14.4
15.6
15.6
2.5
3.6
9.3
9.6
4.1
6.8
2.8
4.0
September 18, 1996 (Version 1.04)
Min
Preliminary
0.9
0
0
0
-2
11.5
12.4
11.0
11.9
12.1
12.4
12.6
13.0
14.0
14.0
Max
2.0
3.6
6.9
7.4
8.1
8.2
8.3
9.8
3.7
6.2
2.8
3.9