XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 72

• Manufacturer Part Number: XC4005L-5PQ208C
• Description: IC 3.3V FPGA 196 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1122

XC4000 Series Field Programmable Gate Arrays
Express Mode (XC4000EX only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers. A CCLK frequency of 1 MHz
is equivalent to a 8 MHz serial rate, because eight bits of
configuration data are loaded per CCLK cycle. Express
mode does not support CRC error checking, but does sup-
port constant-field error checking.
In Express mode, an external signal drives the CCLK input
of the FPGA device. The first byte of parallel configuration
data must be available at the D inputs of the FPGA a short
setup time before the second rising CCLK edge. Subse-
quent data bytes are clocked in on each consecutive rising
CCLK edge.
Express mode is only supported by the XC4000EX and
XC5200 families. It may not be used, therefore, when an
XC4000EX or XC5200 device is daisy-chained with
devices from other Xilinx families.
If the first device is configured in Express mode, additional
devices may be daisy-chained only if every device in the
chain is also configured in Express mode. CCLK pins are
tied together and D0-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or float-
ing, since there is an internal pullup).
accepted only when CS1 is High and the device’s configu-
ration memory is not already full. The status pin DOUT is
pulled Low two internal-oscillator cycles after INIT is recog-
4-76
Figure 63: Express Mode Circuit Diagram
DATA BUS
PROGRAM
CCLK
INIT
X6611
8
4.7K
V
CC
PROGRAM
CS1
D0-D7
INIT
CCLK
M0
XC4000EX/
Frame data is
XC5200
M1
DOUT
DONE
M2
8
nized as High, and remains Low until the device’s configu-
ration memory is full. DOUT is then pulled High to signal
the next device in the chain to accept the configuration data
on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a
large number of devices are included in the chain, deacti-
vate some of the internal pull-ups, since the Low-driving
DONE pin of the last device in the chain must sink the cur-
rent from all pull-ups in the chain. The DONE pull-up is
activated by default. It can be deactivated using a Make-
Bits option.
XC4000EX devices in Express mode are always synchro-
nized to DONE. The device becomes active after DONE
goes High. DONE is an open-drain output. With the DONE
pins tied together, therefore, the external DONE signal
stays low until all devices are configured, then all devices in
the daisy chain become active simultaneously. If the DONE
pin of a device is left unconnected, the device becomes
active as soon as that device has been configured.
XC5200 devices in the chain should be configured as syn-
chronized to DONE (MakeBits option CCLK_SYNC or
UCLK_SYNC), and their DONE pins wired together with
those of the XC4000EX devices.
Express mode must be specified as an option to the Make-
Bits program, which generates the bitstream. The Express
mode bitstream is not compatible with the other six config-
uration modes.
Express mode is selected by a <010> on the mode pins
(M2, M1, M0).
8
CS1
D0-D7
PROGRAM
INIT
CCLK
Daisy-Chained
M0
XC4000EX/
Optional
XC5200
M1
DONE
DOUT
M2
4.7K
September 18, 1996 (Version 1.04)
V
CC
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
To Additional
Optional
Daisy-Chained
Devices
To Additional
Optional
Daisy-Chained
Devices