IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 96

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration
T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Configuration 1
Programming Information
Address: 5CH
Type: Read / Write
Default Value: 010001XX
IDT82V3255
Address: 5DH
Type: Read / Write
Default Value: 00000000
T0_HOLDOVER
MAN_HOLDOV
3 - 2
1 - 0
Bit
7 - 0
7
6
5
4
_FREQ7
Bit
ER
7
7
TEMP_HOLDOVER_MODE[1:0]
T0_HOLDOVER_FREQ[7:0] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
MAN_HOLDOVER
T0_HOLDOVER
AUTO_AVG
AUTO_AVG
READ_AVG
FAST_AVG
_FREQ6
Name
Name
6
6
-
T0_HOLDOVER
FAST_AVG
_FREQ5
Refer to the description of the FAST_AVG bit (b5, 5CH).
Refer to the description of the FAST_AVG bit (b5, 5CH).
This bit, together with the AUTO_AVG bit (b6, 5CH) and the MAN_HOLDOVER bit (b7, 5CH), determines a fre-
quency offset acquiring method in T0 DPLL Holdover Mode.
This bit controls the holdover frequency offset reading, which is read from the T0_HOLDOVER_FREQ[23:0] bits
(5FH ~ 5DH).
0: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is equal to the one written to them.
(default)
1: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is not equal to the one written to them.
The value is acquired by Automatic Slow Averaged method if the FAST_AVG bit (b5, 5CH) is ‘0’; or is acquired by
Automatic Fast Averaged method if the FAST_AVG bit (b5, 5CH) is ‘1’.
These bits determine the frequency offset acquiring method in T0 DPLL Temp-Holdover Mode.
00: The method is the same as that used in T0 DPLL Holdover mode.
01: Automatic Instantaneous. (default)
10: Automatic Fast Averaged.
11: Automatic Slow Averaged.
Reserved.
5
5
MAN_HOLDOVER
0
1
T0_HOLDOVE
READ_AVG
R_FREQ4
4
4
AUTO_AVG
96
0
1
TEMP_HOLDO
T0_HOLDOVE
VER_MODE1
R_FREQ3
don’t-care
3
3
Description
FAST_AVG
Description
don’t-care
TEMP_HOLDO
T0_HOLDOVE
VER_MODE0
0
1
R_FREQ2
2
2
Frequency Offset Acquiring Method
Automatic Slow Averaged (default)
T0_HOLDOVE
R_FREQ1
Automatic Fast Averaged
Automatic Instantaneous
1
1
-
Manual
December 3, 2008
T0_HOLDOVE
R_FREQ0
0
0
-
WAN PLL