IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 85

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

PRIORITY_TABLE1_STS - Priority Status 1 *
Programming Information
IDT82V3255
Address: 4EH
Type: Read
Default Value: 00000000
ORITY_VALIDA
HIGHEST_PRI
7 - 4
3 - 0
Bit
TED3
7
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
ORITY_VALIDA
HIGHEST_PRI
TED2
6
Name
ORITY_VALIDA
HIGHEST_PRI
TED1
5
These bits indicate a qualified input clock with the highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
These bits indicate the T0/T4 selected input clock.
0000: No input clock is selected; or the T4 selected input clock is the T0 DPLL output. (default)
0001, 0010: Reserved.
0011: IN1_CMOS is selected.
0100: IN2_CMOS is selected.
0101: IN1_DIFF is selected.
0110: IN2_DIFF is selected.
0111, 1000: Reserved.
1001: IN3_CMOS is selected.
1010 ~ 1111: Reserved.
ORITY_VALIDA
HIGHEST_PRI
TED0
4
85
CURRENTLY_S
ELECTED_INP
UT3
3
CURRENTLY_S
ELECTED_INP
Description
UT2
2
CURRENTLY_S
ELECTED_INP
UT1
1
December 3, 2008
CURRENTLY_S
ELECTED_INP
UT0
0
WAN PLL