IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 3

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

FEATURES .............................................................................................................................................................................. 9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11
1 PIN ASSIGNMENT ........................................................................................................................................................... 12
2 PIN DESCRIPTION .......................................................................................................................................................... 13
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 17
Table of Contents
3.1 RESET ........................................................................................................................................................................................................... 17
3.2 MASTER CLOCK .......................................................................................................................................................................................... 17
3.3 INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 18
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 19
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 20
3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 22
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 24
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 26
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 28
3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 31
HIGHLIGHTS.................................................................................................................................................................................................... 9
MAIN FEATURES ............................................................................................................................................................................................ 9
OTHER FEATURES ......................................................................................................................................................................................... 9
3.3.1
3.3.2
3.5.1
3.5.2
3.6.1
3.6.2
3.6.3
3.7.1
3.7.2
3.7.3
3.8.1
3.8.2
3.8.3
3.9.1
3.9.2
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 31
Input Clocks .................................................................................................................................................................................... 18
Frame SYNC Input Signals ............................................................................................................................................................ 18
Activity Monitoring ......................................................................................................................................................................... 20
Frequency Monitoring ................................................................................................................................................................... 21
External Fast Selection (T0 only) .................................................................................................................................................. 22
Forced Selection ............................................................................................................................................................................ 23
Automatic Selection ....................................................................................................................................................................... 23
T0 / T4 DPLL Locking Detection ................................................................................................................................................... 24
3.7.1.1
3.7.1.2
3.7.1.3
3.7.1.4
Locking Status ............................................................................................................................................................................... 24
Phase Lock Alarm (T0 only) .......................................................................................................................................................... 25
Input Clock Validity ........................................................................................................................................................................ 26
Selected Input Clock Switch ......................................................................................................................................................... 26
3.8.2.1
3.8.2.2
Selected / Qualified Input Clocks Indication ................................................................................................................................ 27
T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 28
T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 30
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 31
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 31
3.10.1.3 Locked Mode .................................................................................................................................................................... 31
Fast Loss .......................................................................................................................................................................... 24
Coarse Phase Loss .......................................................................................................................................................... 24
Fine Phase Loss ............................................................................................................................................................... 24
Hard Limit Exceeding ....................................................................................................................................................... 24
Revertive Switch ............................................................................................................................................................... 26
Non-Revertive Switch (T0 only) ........................................................................................................................................ 27
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 31
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Table of Contents
December 3, 2008