IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 59

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

INTERRUPTS2_STS - Interrupt Status 2
Programming Information
IDT82V3255
Address: 0EH
Type: Read / Write
Default Value: 00XXXXX1
T0_OPERATING
5 - 1
Bit
7
6
0
_MODE
7
T0_OPERATING_MODE
T0_MAIN_REF_FAILED
IN3_CMOS
T0_MAIN_REF_F
Name
-
AILED
6
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the
T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes.
0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn_CMOS / INn_DIFF
bit (4AH, 4BH).
0: Has not failed. (default)
1: Has failed.
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for IN3_CMOS for T0 path, i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding IN3_CMOS bit (b0, 4BH).
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
5
-
4
-
59
3
-
Description
2
-
1
-
December 3, 2008
IN3_CMOS
0
WAN PLL