IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 39

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

Table 29: Related Bit / Register in Chapter 3.13
Functional Description
IDT82V3255
Figure 10. 0.5 UI Late Frame Sync Input Signal Timing
sync input signal
Selected frame
output signals
Output clocks
T0 selected
Frame sync
input clock
OUTn_PATH_SEL[3:0] (n = 1 or 2)
SYNC_PHn[1:0] (n = 1, 2 or 3)
OUTn_DIVIDER[3:0] (n = 1 or 2)
EX_SYNC_ALARM_MON
2K_8K_PUL_POSITION
AUTO_EXT_SYNC_EN
SYNC_MON_LIMT[2:0]
OUTn_INV (n = 1 or 2)
EX_SYNC_ALARM
EX_SYNC_ALARM
OUT1_PECL_LVDS
IN_SONET_SDH
EXT_SYNC_EN
SYNC_BYPASS
8K_PUL
2K_PUL
8K_INV
2K_INV
8K_EN
2K_EN
Bit
1
2
39
OUT1_FREQ_CNFG, OUT2_FREQ_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
OUT1_INV_CNFG, OUT2_INV_CNFG
Figure 11. 1 UI Late Frame Sync Input Signal Timing
INTERRUPTS3_ENABLE_CNFG
sync input signal
Selected frame
output signals
Output clocks
Frame sync
T0 selected
input clock
SYNC_MONITOR_CNFG
FR_MFR_SYNC_CNFG
SYNC_PHASE_CNFG
INPUT_MODE_CNFG
INTERRUPTS3_STS
OPERATING_STS
Register
December 3, 2008
Address (Hex)
71, 6D
73, 72
0A
7C
7D
09
74
52
0F
12
WAN PLL