IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 106

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration
Programming Information
IDT82V3255
Address:74H
Type: Read / Write
Default Value: 01100000
IN_2K_4K_8K_I
Bit
7
6
5
4
3
2
1
0
NV
7
2K_8K_PUL_POSITION
IN_2K_4K_8K_INV
8K_PUL
2K_PUL
8K_INV
2K_INV
8K_EN
2K_EN
Name
8K_EN
6
This bit determines whether the input clock is inverted before locked by the T0/T4 DPLL when the input clock is 2 kHz, 4
kHz or 8 kHz.
0: Not inverted. (default)
1: Inverted.
This bit determines whether an 8 kHz signal is enabled to be output on FRSYNC_8K.
0: Disabled. FRSYNC_8K outputs low.
1: Enabled. (default)
This bit determines whether a 2 kHz signal is enabled to be output on MFRSYNC_2K.
0: Disabled. MFRSYNC_2K outputs low.
1: Enabled. (default)
This bit is valid only when FRSYNC_8K and/or MFRSYNC_2K output pulse; i.e., when one of the 8K_PUL bit (b2, 74H)
and the 2K_PUL bit (b0, 74H) is ‘1’ or when the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) are both ‘1’. It deter-
mines the pulse position referring to the standard 50:50 duty cycle.
0: Pulsed on the falling edge of the standard 50:50 duty cycle position. (default)
1: Pulsed on the rising edge of the standard 50:50 duty cycle position.
This bit determines whether the output on FRSYNC_8K is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on FRSYNC_8K is 50:50 duty cycle or pulsed.
0: 50:50 duty cycle. (default)
1: Pulsed. The pulse width is defined by the period of the output on OUT2.
This bit determines whether the output on MFRSYNC_2K is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on MFRSYNC_2K is 50:50 duty cycle or pulsed.
0: 50:50 duty cycle. (default)
1: Pulsed. The pulse width is defined by the period of the output on OUT2.
2K_EN
5
2K_8K_PUL_P
OSITION
4
106
8K_INV
3
Description
8K_PUL
2
2K_INV
1
December 3, 2008
2K_PUL
0
WAN PLL