IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 35

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

Table 23: Related Bit / Register in Chapter 3.11
3.11.5.2
locking. The output can be derived from the 77.76 MHz path or the
Functional Description
Note: * The setting in the 5A register is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
IDT82V3255
The four paths for T4 DPLL output are as follows:
T4 selected input clock is compared with a T4 DPLL output for DPLL
• 77.76 MHz path - outputs a 77.76 MHz clock;
• 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by
• GSM/GPS/16E1/16T1 path - outputs a GSM, GPS, 16E1 or
• 12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock,
the IN_SONET_SDH bit;
16T1 clock, as selected by the T4_GSM_GPS_16E1_16T1_
SEL[1:0] bits;
as selected by the T4_12E1_24T1_E3_T3_SEL[1:0] bits.
T4 Path
T0_GSM_OBSAI_16E1_16T1_SEL[1:0]
T4_GSM_GPS_16E1_16T1_SEL[1:0]
T0_12E1_24T1_E3_T3_SEL[1:0]
T4_12E1_24T1_E3_T3_SEL[1:0]
PH_TR_MON_LIMT[3:0]
PH_MON_PBO_EN
PH_OFFSET_EN
PH_OFFSET[9:0]
T4_TEST_T0_PH
IN_SONET_SDH
MULTI_PH_APP
PH_MON_EN
T4_T0_SEL
PBO_FREZ
PBO_EN
T0_LIMT
Bit
PHASE_OFFSET[9:8]_CNFG, PHASE_OFFSET[7:0]_CNFG
35
PHASE_LOSS_COARSE_LIMIT_CNFG
16E1/16T1 path. In this case, the output path is automatically selected
and the output is automatically divided to get the same frequency as the
T4 selected input clock.
input clock to get the phase difference between T0 and T4 selected input
clocks, as determined by the T4_TEST_T0_PH bit.
cess.
In addition, T4 selected input clock is compared with the T0 selected
T4 DPLL outputs are provided for T0/T4 APLL or device output pro-
T0_BW_OVERSHOOT_CNFG
T0_DPLL_APLL_PATH_CNFG
T4_DPLL_APLL_PATH_CNFG
PHASE_OFFSET[9:8]_CNFG
PHASE_MON_PBO_CNFG
T4_T0_REG_SEL_CNFG
MON_SW_PBO_CNFG
T4_INPUT_SEL_CNFG
INPUT_MODE_CNFG
Register
December 3, 2008
Address (Hex)
7B, 7A
5A *
0B
7B
59
78
09
55
60
51
07
WAN PLL