IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 93

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration
T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration
Programming Information
IDT82V3255
Address: 58H
Type: Read / Write
Default Value: 01101111
Address: 59H
Type: Read / Write
Default Value: 1XXX1XXX
T0_DPLL_LOCK
ED_DAMPING2
AUTO_BW_SEL
7 - 5
4 - 0
6 - 4
2 - 0
Bit
Bit
7
3
7
7
T0_DPLL_LOCKED_DAMPING[2:0]
AUTO_BW_SEL
T0_DPLL_LOCKED_BW[4:0]
T0_DPLL_LOCK
ED_DAMPING1
T0_LIMT
Name
-
-
6
6
-
Name
This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL.
0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used
regardless of the T0 DPLL locking stage.
1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking
stages. (default)
Reserved.
This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached.
0: Not frozen.
1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default)
Reserved.
T0_DPLL_LOCK
ED_DAMPING0
5
5
-
These bits set the locked damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
These bits set the locked bandwidth for T0 DPLL.
00XXX: Reserved.
01000: 0.1 Hz.
01001: 0.3 Hz.
01010: 0.6 Hz.
01011: 1.2 Hz. (default)
01100: 2.5 Hz.
01101: 4 Hz.
01110: 8 Hz.
01111: 18 Hz.
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 11111: Reserved.
T0_DPLL_LOC
KED_BW4
4
4
-
93
T0_DPLL_LOC
KED_BW3
T0_LIMT
3
3
Description
Description
T0_DPLL_LOC
KED_BW2
2
2
-
T0_DPLL_LOC
KED_BW1
1
1
-
December 3, 2008
T0_DPLL_LOC
KED_BW0
0
0
-
WAN PLL